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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
Table 10: Mode Register Assignments
Notes 1–5 apply to all parameters and conditions
MR#
MA[7:0]
Function
Access
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Link
0
1
00h
01h
Device info
Device feature 1
R
W
RFU
n WR (for AP)
RZQI
WC
BT
DNVI
DI
BL
DAI
go to MR0
go to MR1
2
3
02h
03h
Device feature 2
I/O config-1
W
W
RFU
RFU
RL and WL
DS
go to MR2
go to MR3
4
04h
SDRAM refresh
R
TUF
RFU
Refresh rate
go to MR4
rate
5
6
7
05h
06h
07h
Basic config-1
Basic config-2
Basic config-3
R
R
R
LPDDR2 Manufacturer ID
Revision ID1
Revision ID2
go to MR5
go to MR6
go to MR7
8
9
10
11–15
16
17
18–19
08h
09h
0Ah
0Bh ≈ 0Fh
10h
11h
12h–13h
Basic config-4
Test mode
I/O calibration
Reserved
PASR_Bank
PASR_Seg
Reserved
R
W
W
–
W
W
–
I/O width
Density
Vendor-specific test mode
Calibration code
RFU
Bank mask
Segment mask
RFU
Type
go to MR8
go to MR9
go to MR10
go to MR11
go to MR16
go to MR17
go to MR18
20–31
14h–1Fh
Reserved for NVM
MR20–MR30
32
20h
DQ calibration
R
See Table 47 (page 90).
go to MR32
pattern A
33–39
21h–27h
Do not use
go to MR33
40
28h
DQ calibration
R
See Table 47 (page 90).
go to MR40
pattern B
41–47
29h–2Fh
Do not use
go to MR41
48–62
63
64–126
127
30h–3Eh
3Fh
40h–7Eh
7Fh
Reserved
RESET
Reserved
Do not use
–
W
–
RFU
X
RFU
go to MR48
go to MR63
go to MR64
go to MR127
128–190
191
192–254
255
80h–BEh
BFh
C0h–FEh
FFh
Reserved for vendor use
Do not use
Reserved for vendor use
Do not use
RVU
RVU
go to MR128
go to MR191
go to MR192
go to MR255
Notes:
1. RFU bits must be set to 0 during MRW.
2. RFU bits must be read as 0 during MRR.
3. For READs to a write-only or RFU register, DQS will be toggled and undefined data is
returned.
4. RFU mode registers must not be written.
5. WRITEs to read-only registers must have no impact on the functionality of the device.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
44
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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